With the ever-increasing need for increased battery life for battery-powered devices, the need for low-power systems and SOCs (system on a chip) is also increasing. This gives rise to the need for power-managed designs with multiple power/voltage domains. In a design having a power domain, often there is a requirement to preserve state (of a flip-flop) even while the power domain is switched off. This state, often known as the standby state, helps reduce power-down and power-up time. To preserve this state, retention flops are widely used in almost all power-managed SOCs.
A typical retention flop includes a master latch and a slave latch, with the slave latch storing the state during power down. The slave latch of a retention flop must be powered by an always-on (AON) retention supply to store data when the associated device is turned off. The n-well and drain of the slave latch must to be connected to the always-on supply. To reduce leakage, the slave latch is often designed with high-voltage-threshold (HVT) transistors, while the master-latch is implemented using standard-voltage-threshold (SVT) transistors to target performance. Thus, such HVT transistors will at times be referred to herein as AON logic and such SVT transistors as switchable logic.
N-well leakage of SVT transistors is quite higher than that of HVT transistors. The n-well and drain of the storing latch of a retention flop must be connected to an always-on power supply, whereas the n-well and drain of the master latch of the retention flop should be connected to a switchable power supply in order to limit leakage current during retention/stand-by mode. Since the n-wells of the master latch and slave latch of the logic cell are connected to two different power supplies, such a logic cell must have two separate n-wells, which will also be referred to herein as a split n-well.
FIG. 1 is a schematic circuit diagram of an illustrative retention flop. Note that the retention flop implementation shown in FIG. 1 is merely illustrative and that any number of different implementations are possible. The retention flop 100 of FIG. 1 is a D flip-flop and includes a master latch 110 and a slave latch 120. The illustrative master latch 110 of FIG. 1 includes inverter 112, inverter 114 and inverter 116. Slave latch 120 includes inverter 122 and inverter 124. The master latch 110 captures a new value D at the input to inverter 112, while the slave latch 120 retains the value that was previously received by the master latch 110. A pass gate 130 passes the value held in the master latch 110 to the slave latch 120 dependent upon a clock signal CK. Each of the inverters 112, 114, 116, 122, 124, and 135 are illustratively composed of one or more transistors, such as metal oxide semiconductor (MOS) transistors. Together, the master latch 110, slave latch 120, pass gate 130, and inverter 135 make up what is often referred to as a logic cell. In general, the term logic cell, as used herein, refers to a functional grouping of electronic elements such as transistors that form a logic element such as the D flip-flop of FIG. 1.
The master latch 110 is coupled to the always-on power supply VDDC via a power switch 140. The master latch 110 is illustratively disconnected from the power supply VDDC by power switch 140 when the device is turned off or placed in a stand-by state in order to conserve battery power. In contrast, the slave latch 120 is connected directly to the always-on power supply VDDC in order to maintain the data contents stored by the slave latch even when the device is turned off or placed in a standby state. Thus in device implementations wherein the master latch 110 and slave latch 120 are comprised of MOS transistors, the n-wells of the master latch transistors are coupled to the always-on power supply VDDC via power switch 140, while the n-wells of the slave latch transistors are connected directly to the always-on power supply VDDC. In alternative implementations, the master latch 110 is connected to a different, switchable, power supply, rather than connected to an always-on supply via a power switch. Since the n-wells of the master latch 110 and slave latch 120 of the logic cell 100 are connected to two different power supplies, such a logic cell must have two separate n-wells.
FIG. 2 is a schematic top view of an integrated circuit power domain. FIG. 2 shows typical placement of standard logic cells in such a power domain. The power domain block 200 includes a p-well plane 220 comprised of positively doped (p+) semiconductor material. The power domain block 200 is conceptually divided into multiple rows, commonly referred to as cell rows 202, 204, 206, 208, 210, 212. The power domain block 200 further includes a plurality of substantially parallel n-well drawings 230, 232, 234, each comprising a layer of negatively doped (n+) semiconductor material deposited on top of the p-well-plane 220. Such n-well drawings 230, 232, and 234 will be alternatively referred to as n-well rows herein. Typically two adjacent cell rows share a common n-well drawing, with one cell row being flipped (sometimes referred to as a south row) and the other cell row not being flipped (sometimes referred to as a north row). For example, in FIG. 2, cell row 202 shares n-well row 230 with cell row 204, cell row 206 shares n-well row 232 with cell row 208, and cell row 210 shares n-well row 234 with cell row 212. Thus standard logic cell 240 shares n-well 234 with standard logic cell 242. Double-height standard logic cell 244 also makes use of n-well 234 as well as n-well 232. Double-height power switch cell 250 utilizes only n-well 232, which falls fully inside the footprint of the power switch cell 250, as opposed to the power switch cell 250 sharing n-well 232 with an adjacent flipped cell row. FIG. 2 also shows power tap cells 260-280 which are electrically coupled to the n-well rows 230, 232, 234 and also coupled to a power source to provide power to the n-wells 230, 232, 234. For example, n-well row 230 is coupled to tap cells 260, 266, 270 and 276; n-well row 232 is coupled to tap cells 262, 268, 272 and 278; and n-well row 234 is coupled to tap cells 264, 270, and 280. Each n-well row 230, 232, 234 has tap cells placed at regular intervals along its length in order to minimize voltage drops resulting from resistive losses.
In the illustrative power domain block 200 of FIG. 2, all of the n-wells are connected to the same power supply. But in cases where a logic cell requires access to two different power supplies, such as in the example of FIG. 1, where the master latch 110 is powered by a switchable power supply and the slave latch 120 is powered by an always-on power supply, such a cell has to have two different n-wells that are separated from each other. Various solutions exist for implementing such n-well separation. One such existing solution is shown in FIG. 3. FIG. 3 is a schematic diagram of a double-height logic cell 300 occupying two adjacent cell rows 310 and 312. Logic cell 300 is commonly referred to as a “double-height” logic cell although the dimension occupied by the two logic cell rows 310 and 312 does not necessarily represent “height” in the traditional sense but may also represent other dimensions such as width or length. In the solution represented by FIG. 3, the standard-voltage-threshold (SVT) logic of the master latch of logic cell 300 is situated proximate, and utilizes, the n-well row 320. N-well row 320 is coupled to a power switch 330 via one or more tap cells (not shown) that are placed at regular intervals along the length of n-well row 320 as shown in FIG. 2. The power switch 330 selectably couples the SVT n-well row 320 to an always-on power supply VDDC. Alternatively, the SVT n-well row 320 can be coupled to a switchable power supply that is wholly independent of the always-on power supply VDDC. A second n-well 340 is situated fully contained within, but isolated from, the n-well row 320. The high-voltage-threshold (HVT) logic of the slave latch of logic cell 300 is situated proximate, and utilizes, this second n-well 340. HVT n-well 340 is coupled to the always-on power supply VDDC. An AON tap cell 350 is placed inside each logic cell, illustratively situated within the footprint of the HVT n-well 340, coupling the HVT n-well 340 to the always-on power supply VDDC.
The prior art solution represented by FIG. 3 requires an area increase of the retention cell. The power domain of the n-well row 320 is switchable; thus to prevent a spacing requirement from an adjacent cell, the always-on n-well 340 is sandwiched between switchable n-wells. The AON tap connection requires extra area inside the cell 300 to accommodate the tap-cell 350 and maintain spacing between n-well 320 and n-well 340. Such an implementation is also susceptible to latch-up issues due to the narrow n-well connection between the switchable n-well islands 360 and 370.
Another prior art n-well separation solution is shown in FIG. 4. FIG. 4 is a schematic diagram of a double-height logic cell 400 occupying two adjacent cell rows 410 and 412. In the solution represented by FIG. 4, one side of logic cell 400 has a switchable n-well 420 while another side of the cell 400 has an always-on n-well 440. The standard-voltage-threshold logic of the master latch of logic cell 400 is situated proximate, and utilizes, the switchable n-well 420, which is coupled to a switchable power supply 430 via a tap cell (not shown) that, in some implementations, is coupled to the n-well 420 outside of the footprint of the logic cell 400. The high-voltage-threshold logic of the slave latch of logic cell 400 is situated proximate, and utilizes, the always-on n-well 440, which is coupled to an always-on power supply VDDC via a tap cell (not shown) that, in some implementations, is coupled to the n-well 440 outside of the footprint of the logic cell 400. An advantage of the n-well separation solution of FIG. 4 is that adjacent cells can be arranged “flipped” relative to each other. For example, a cell to the right of logic cell 400 can be arranged such that it shares the always-on n-well 440 with logic cell 400, and a cell to the left of logic cell 400 can be arranged such that it shares the switchable n-well 420 with logic cell 400. But since the n-wells 420 and 440 are not continued, the solution of FIG. 4 requires tap cells between standard logic cells, which increases the area required by this solution. Additionally, the n-well spacing between the two n-wells 420 and 440 needs to be maintained within the cell, further increasing the area requirement.